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IRDC3870
SupIRBuck
DESCRIPTION
TM
USER GUIDE FOR IRDC3870 EVALUATION BOARD
The IR3870 SupIRBuckTM is an easy-to-use, fully integrated and highly efficient DC/DC voltage regulator. The onboard constant on time hysteretic controller and MOSFETs make IR3870 a space-efficient solution that delivers up to 10A or precisely controlled output voltage in 60C ambient temperature applications without airflow. It is housed in a in 20 Lead 5mmx6mm QFN package. Key features offered by the IR3870 include: programmable switching frequency, soft start, and over current protection allows for a very flexible solution suitable for many different applications and an ideal choice for battery powered applications.
Additional features include pre-bias startup, very precise 0.5V reference, over/under voltage shut down, power good output, and enable input with voltage monitoring capability. This user guide contains the schematic and bill of materials for the IRDC3870 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed specifications and application information for IR3870 is available in the IR3870 data sheet.
BOARD FEATURES * Vin = +12V Typical ( 8-19V input Voltage range. see note below)
* PVcc= +5.0V * Vcc=+3.3V
* Vout = +1.1V @ 0- 10A
* Fs = 500kHz @ 10A
* L = 0.56uH * Cin= 1x10uF (ceramic 1210) + 1x68uF (electrolytic) * Cout= 2x10uF (ceramic 0805) + 1x150uF(SP Cap)
Note: At low input line an additional 10uF ceramic capacitor is recommended at input to handle higher ripple current)
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IRDC3870
CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN and PGND. A maximum 10A load should be connected to VOUT and PGND. The connection diagram is shown in Fig. 1 and inputs and outputs of the board are listed in Table I. IRDC3870 has three input connectors, one for biasing (PVcc),one for biasing Vcc and the third one as input voltage (Vin). Separate supplies should be applied to these inputs. PVcc input should be a well regulated 4.5V-5.5V supply and it would be connected to PVcc and PGND and Vcc input should be a well regulated 3.0V-3.6V supply and it would be connected to Vcc and PGND. An external signal can be provided as Enable signal to turn on or turn off the converter. The absolute maximum voltage of Enable signal is +3.9V. A well regulated 0-2V signal source is used in this user guide. The evaluation board is configured for use with 2x10uF (ceramic 0805) + 1x150uF (SP) capacitors. However, the design can be modified for an all ceramic output cap configuration by adding the inductor DCR sensing circuit as show in the schematic on page 8. Table I. Connections
Connection VIN (TP53) PGND (TP55) PVcc+ (TP61) Vcc+ (TP59) PGND (TP62) PGND (TP60) VOUT (TB5) PGND (TB6) Enable (TP52) Signal Name VIN (+12V) Ground of VIN PVcc input (+5.0V) PVcc input (+3.3V) Ground for PVcc input Ground for Vcc input Vout (+1.1V) Ground of Vout Enable input
LAYOUT
The PCB is a 4-layer board. All layers are 2 Oz. copper. The IR3870 and other components are mounted on the top and bottom side of the board. Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located close to IR3870. The feedback resistors are connected to the output voltage at the point of regulation and are located close to IR3870. To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground current path.
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IRDC3870
Connection Diagram
Vin = +12V
GROUND
Enable
GROUND
Vcc = +3.3V
PVcc = +5.0V GROUND
GROUND
VOUT = +1.1V
Fig. 1: Connection diagram of IRDC3870 evaluation board
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IRDC3870
PCB Board Layout
Fig. 2: Board layout, top layer
Fig. 3: Board layout, bottom layer
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IRDC3870
PCB Board Layout
Fig. 4: Board layout, mid-layer I
Fig. 5: Board layout, mid-layer II
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IRDC3870
6
Fig.6: Schematic of the IRDC3870 evaluation board
IRDC3870
Bill of Materials
Reference
C85 C84,C86 C87 C89 C90 C96 C92,C101,C103 C93,C94 C98 C91,C95,C100,C102,C109 C104,C105,C106,C107 C108 D8 D9 L3 R92,R97 R93,R98,R100,R102 R94 R95 R96 R101 R103 R104 R105,R106 U6
Quantit y
1 2 1 1 1 1 3 2 1 5 4 1 1 1 1 2 4 1 1 1 1 1 1 2 1
Value
0.1uF 1uF 10uF 150uF 47pF 150uF DNI 10uF 22nF DNI 1uF DNI MBR0530 BAT54S 0.56uH,4.0mOhm 10K 0 2 124K 6.81K DNI 1.96k 1.65K DNI IR3870
Description
CAP,CER,0.1UF,50V,10%,X7R,0603 CAP,CER,1.0UF,25V,X7R,0603 CAP,10UF,25V,CERAMIC,X5R,1210 CAP,150UF,35V,ELECT,FK,SMD CAP,CER,47PF,50V,5%,C0G,0603 CAP ,Polymer,150uF 4V
Part-Number
GRM188R71H104KA93D ECJ-3YB1E105K ECJ-4YB1E106M EEEFK1V101XP GRM1885C1H470JA01D EEFCX0G151R
Manufacturer
Murata Panasonic Panasonic Panasonic Murata Panasonic
CAP,CER,10UF,6.3V,10%,X5R,0805 CAP,CER,22000PF,50V,10%,X7R,0603
GRM21BR60J106KE19L GRM188R71H223KA01D GRM31CF50J107ZE01L
Murata Murata Murata Taiyo Yuden kemet On Semiconductor NXP Semiconductors ACT Rohm Semiconductor Rohm Semiconductor AVX AVX Panasonic
CAP,CER,1.0UF,16V,X7R,0603 CAP,1000PF,50V,CERAMIC,X7R,0603 DIODE,SCHOTTKY,30V,0.5A,SOD123 DIODE,SCHOTTKY,30V,DUAL,SOT23 SMT Power Inductor RES,10.0K,OHM,1/10W,1%,0603,SMD RES,0.0,OHM,1/8W,5%,0805,SMD RES,2.00,OHM,1/10W,1%,0603,SMD RES,124,OHM,1/10W,1%,0603,SMD RES,6.80K,OHM,1/10W,1%,0603,SMD
EMK107BJ105KA-TR C0603C102K5RACTU MBR0530T1G BAT54S-T/R MSQ1006-R56N-R MCR03EZPFX1002 MCR10EZPJ000 RC0603FR-072RL RC0603FR-07124RL ERJ-3EKF6801V
RES,1.96K,OHM,1/10W,1%,0603,SMD RES,1.65K,OHM,1/10W,1%,0603,SMD
ERJ-3EKF1961V ERJ-3EKF1651V
Panasonic Panasonic
IR
7
IRDC3870
8
Fig.7: Schematic of the IRDC3870 using all Ceramic Output Capacitor
IRDC3870
Bill of Materials with all Ceramic output Capacitors
Quantit y 2 2 1 1 1 4 3 3 1 1 2 4 1 1 1 2 4 1 1 1 1 3 1 1 1
Reference C85,C97 C84,C86 C87 C89 C90 C93,C95,C100,C108 C92,C101,C103 C94,C96,C109 C98 C99 C91,C102 C104,C105,C106,C107 D8 D9 L3 R92,R97 R93,R98,R100,R102 R94 R95 R96 R99 R101,R105,R106 R103 R104 U6
Description CAP,CER,0.1uF,50V,10%,X7R,0603 CAP,CER,1.0uF,25V,X7R,0603 CAP,10uF,25V,CERAMIC,X5R,1210 CAP,68uF,25V,ELECT,FK,SMD CAP,CER,47pF,50V,5%,C0G,0603 DNI CAP,CER,100uF,6.3V,X5R,1210 DNI CAP,CER,22000pF,50V,10%,X7R,0603 CAP,CER,1000pF,50V,5%,C0G,0603 CAP,CER,47uF,6.3V,X5R,0805 CAP,CER,1.0uF,16V,X7R,0603 DIODE,SCHOTTKY,30V,0.5A,SOD123 DIODE,SCHOTTKY,30V,DUAL,SOT23 INDUCTOR,FERRITE,220nH,20%,25A,0.39mOhm,SMD RES,10.0K,OHM,1/10W,1%,0603,SMD RES,0.0,OHM,1/8W,5%,0805,SMD RES,2.00,OHM,1/10W,1%,0603,SMD RES,93.1K,OHM,1/10W,1%,0603,SMD RES,6.80K,OHM,1/10W,1%,0603,SMD RES,4.02K,OHM,1/10W,1%,0603,SMD DNI RES,1.96K,OHM,1/10W,1%,0603,SMD RES,1.65K,OHM,1/10W,1%,0603,SMD IR3870
Part-Number GRM188R71H104KA93D ECJ-3YB1E105K ECJ-4YB1E106M EEV-FK1E680P GRM1885C1H470JA01D
Manufacturer Murata Panasonic Panasonic
Murata
C3225X5R0J107M
TDK
GRM188R71H223KA01D GRM1885C1H102JA01D JMK212BJ476MG-T EMK107BJ105KA-TR MBR0530T1G BAT54S-T/R PA0511.221NLT MCR03EZPFX1002 MCR10EZPJ000 RC0603FR-072RL CRCW060393K1FKEA ERJ-3EKF6801V CRCW06034K02FKEA
Murata Murata Taiyo Yuden Taiyo Yuden On Semiconductor NXP Semiconductor Pulse Engineering Rohm Semiconductor Rohm Semiconductor AVX Vishay Panasonic Vishay
ERJ-3EKF1961V ERJ-3EKF1651V
Panasonic Panasonic
9
IRDC3870
TYPICAL OPERATING WAVEFORMS Vin=12V, PVcc=5.0V, Vcc=3.3V,Vo=1.1V, Io=0- 10A, , Room Temperature, No Air Flow
CH1: Vout (50mV/div); CH2: Phase (10V/div) CH4: CPO (2V/div); Time: 2uS/div) Figure 8: Charge Pump Off at Iout = 1A
CH1: Vout (50mV/div); CH2: Phase (10V/div) CH4: CPO (2V/div); Time: 2uS/div) Figure 9: Charge Pump On at Iout =3A
CH1: Vout (50mV/div); 20uS/div CH2: Phase (10V/div) Figure 10: Load Step (2A to 10A) Transient (5A/uS) at 19Vin with 50mV Overshoot
CH1: Vout (50mV/div); 20uS/div CH2: Phase (10V/div) Figure 11: Load Step (2A to 10A) Transient (5A/uS) at 12Vin with 50mV Overshoot
Note1: Enable is provided by an external signal (0-2.0V) after Vin=12V and PVcc=5.0V are applied. Note2: Vo ripple is measured across the output capacitor.
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IRDC3870
TYPICAL OPERATING WAVEFORMS Vin=12V, PVcc=5.0V, Vcc=3.3V,Vo=1.1V, Io=0- 10A, , Room Temperature, No Air Flow
CH1: Vout (50mV/div); 20uS/div CH2: PHASE (10V/div) Figure 12: FCCM/CCM transition from 0.5A to 5A at 19Vin
CH1: Vout (50mV/div); 20uS/div CH2: PHASE (10V/div) Figure 13: FCCM/CCM transition from 0.5A to 5A at 12Vin
CH1: Vout (500mV/div); 500uS/div CH2: PHASE (10V/div) CH3: EN (2V/div) CH4: PGOOD (5V/div) Figure 14: Startup/Shutdown 12Vin at 500mA
CH1: Vout (500mV/div); 500uS/div CH2: PHASE (10V/div) CH3: EN (2V/div) CH4: PGOOD (5V/div) Figure 15: Startup/Shutdown 12Vin at 3A
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IRDC3870
TYPICAL OPERATING WAVEFORMS Vin=12V, PVcc=5.0V, Vcc=3.3V, Vo=1.1V, Io=0- 10A, , Room Temperature, No Air Flow
Ef f-19Vin w /CP Ploss-19Vin w /CP Eff-19Vin no CP Ploss-19Vin no CP
88 87 86
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 2 4 6 8 10 12
85 84 83 82 81 80
Output Current(A)
Figure 16: Typical Efficiency and Power Loss of Converter Vout = 1.1V
Vout Regulation
1.1110 1.1105 1.1100 O u tp u t Vo ltag e (V) 1.1095 1.1090 1.1085 1.1080 1.1075 1.1070 1.1065 1.1060 1.1055 0 2 4 6 8 10 Output Current (A) 19Vin 12.6Vin
Figure 17: Typical Output Voltage Regulation
Power Loss (W)
Efficiency (%)
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IRDC3870
TYPICAL OPERATING WAVEFORMS Vin=12V, PVcc=5.0V, Vcc=3.3V, Vo=1.1V, Io=0- 10A, , Room Temperature, No Air Flow
IC: 69C, Inductor: 51C, PCB: 51C Figure 18: Thermal Image @12Vin, 10A, Ta= 25C and no air flow
IC: 75C, Inductor: 53C, PCB: 54C Figure 19: Thermal Image @19Vin, 10A, Ta= 25C and no air flow
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IRDC3870
PCB Metal and Components Placement
Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to lead spacing should be 0.2mm to minimize shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The outboard extension ensures a large toe fillet that can be easily inspected. Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. Copper or no less than 0.1mm for 1 oz. Copper or no less than 0.23mm for 3 oz. Copper.
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IRDC3870
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignment. Ensure that the solder resist in between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
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IRDC3870
Stencil Design
The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much solder is deposited on the center pad the part will float and the lead lands will open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste.
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IRDC3870
Mechanical Outline Drawing
DIM A A1 b b1 c D E e e1 e2
MILIMITERS MIN MAX 0.8 1 0 0.05 0.375 0.475 0.25 0.35 0.203 REF. 5.000 BASIC 6.000 BASIC 1.033 BASIC 0.650 BASIC 0.852 BASIC
INCHES MIN MAX 0.0315 0.0394 0 0.002 0.1477 0.1871 0.0098 0.1379 0.008 REF. 1.970 BASIC 2.364 BASIC 0.0407 BASIC 0.0256 BASIC 0.0259 BASIC
DIM L M N O P Q R S t1, t2, t3 t4 t5
MILIMITERS MIN MAX 0.35 0.45 2.441 2.541 0.703 0.803 2.079 2.179 3.242 3.342 1.265 1.365 2.644 2.744 1.5 1.6 0.401 BASIC 1.153 BASIC 0.727 BASIC
INCHES MIN MAX 0.0138 0.0177 0.0962 0.1001 0.0277 0.0314 0.0819 0.0858 0.1276 0.1316 0.0498 0.05374 0.1042 0.1081 0.0591 0.063 0.016 BACIS 0.045 BASIC 0.0286 BASIC
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 07/16/09 17

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